It is well-known that with increasing circuit densities, timing requirements, and bus capacities in integrated circuit chips, wiring widths must be decreased. Decreased wiring widths, however, leads to increased resistances, impacting the slew rate and path delay of the wiring. Wiring must comply with a maximum slew rate and minimum delay based on the required timing. This wiring problem is aggravated when macro “blocks” occupy otherwise open space on the integrated circuit plan. These macros often interfere with subsequently-designed wiring paths which must comply with the slew rate and delay requirements.
To illustrate these problems, and with reference to FIG. 1, an IC 10 may include an embedded macro 12 having remnant silicon and/or wiring whitespace areas 241 . . . 244. Assume that IC wiring is required from region 14 to region 16 of the IC. Running wiring across the macro may not be possible, since design tools usually see the macro as a fixed block, which cannot be modified when placing and routing the higher level IC wiring. Even assuming that whitespace is available and recognized by the design tools, running a standard width wire 18 across the macro may not suffice, since the distance over which this wire is run (i.e., the horizontal width of the macro 12) may exceed that required for the maximum slew rate and delay.
Another option involves re-routing the wiring around the macro along the longer path 20, and using repowering circuits 221 . . . 225 to maintain the required slew rate and path delays while compensating for the excess path length. This approach, however, involves the use of valuable silicon area and power to support the repowering circuits, and may not be sufficient to meet path delay requirements.
What is required, therefore, are techniques for maintaining the required wiring slew rates and path delays across an entire IC in the presence of large, fixed macro blocks.